1. Field of the Disclosure
The present invention generally relates to bulk metal-oxide semiconductor field-effect transistors (MOSFETS) and silicon-on-insulator (SOI) MOSFETs and specifically, a self-aligned silicide (salicide) process for thin film SOI MOSFETs having low resistivity contacts and a self-aligned silicide (salicide) process for shallow junctions.
2. Description of the Related Art
Conventionally, a reduction of a short channel effect in a silicon-on-insulator (SOI) MOSFET has been addressed by using ultra-thin silicon films (e.g., having a thickness substantially within a range of about 50 nm to about 3 nm). However, using an ultra-thin SOI film can result in high source/drain series resistance. A portion of the high source/drain series resistance can be reduced by using a self-aligned silicide (salicide) contact (e.g., for a discussion of salicides, see Lisa T. Su et al., “Optimization of the series resistance in sub-0.2 fim SOI MOSFET's”, Electron Device Letters, 15(9), p. 363, September 1994 and U.S. Pat. No. 6,987,050).
The conventional salicide process has been limited to bulk or thick SOI films (e.g., for purposes of this disclosure, a “bulk” or “thick” SOI film is thicker than 100 nm). Reduction of a SOI film thickness to an estimated 10 nm precludes the use of conventional salicide. That is, if the amount of silicon consumed by the formation of the silicide alloy becomes a large portion of the initial SOI film thickness, then the contact area will decrease, leading to an increase in the contact resistance. Further, even if a conventional salicide was used with thin films, there is no guarantee of low parasitic resistance because an ultra-thin silicon film may be completely consumed during the silicide formation. Further, the conventional salicide process can form a metal-rich silicide which is characterized by higher resistance, if there is not enough silicon to complete the reaction that forms the low resistivity silicide phase.
In the case of a thin SOI film, the percentage of the SOI consumed by the silicide considerably affects the series resistance. It has been demonstrated that when 80% or more of the SOI layer is consumed, the series resistance begins to increase as a result of a reduction in the contact area (e.g., see Su et al., supra).
Alternatively, if the silicide layer is made extremely thin (e.g., less than 30 nm) to avoid consuming the thin SOI film, then the silicide layer loses its efficiency in reducing the series resistance. For example, if the silicide is in the thick regime, then a reduction of the silicide thickness would roughly yield a proportional increase in the series resistance. This linear behavior would hold down to about 20 nm (depending on the silicide metal). A thinner silicide film may exhibit nucleation problems and some of the phases may not form. All of this would lead to a very steep increase in the contact resistance.
The series parasitic resistance should be minimized to facilitate the fabrication of high performance thin film SOI MOSFETs. The conventional salicide process is not applicable to the production of ultra-thin SOI MOSFETs, and therefore a new salicide process is required to overcome the problems of the conventional method. Further, the conventional method and structures are deficient in their silicide/SOI interface roughness.
Yet another problem of the conventional structures and methods is associated with shallow junctions used in both bulk and SOI MOSFET structures. That is, shallow junctions provide many benefits when used with the fabrication of submicron MOSFET. For example, they allow for a large punch-through voltage. That is, the lateral spread of the source and drain depletion regions below the surface layer makes a MOSFET more prone to punch-through. Therefore, shallow source and drains effectively suppress subsurface punch-through path.
Additionally, shallow junctions provide better short channel behavior, and in particular less Vr roll-off (e.g., see S. Wolf, Silicon Processing for the VLSI Era, Volume 3—The Submicron MOSFET, Lattice Press, 1995).
Additionally, such shallow junctions allow for steeper junction (dopant) profiles. For example, low energy implants are used to form shallow junctions. The lateral projection range decreases with the implant energy, and therefore more abrupt junctions can be obtained.
To reduce the series resistance to the source and drain, a self-aligned (salicide) process may be used in the fabrication of the MOSFET device. The top surface of the source and drain regions are silicided, by converting some of the superficial Si into silicide phases such as CoSi2, or TiSi2.
The conventional salicide process typically comprises the following process. First, blanket deposition of a metal such as Co, Ti or Ni, is performed. For example, the typical required film thickness for Co is about 8 nm. The Co deposition is followed by a TiN cap deposition of about 20 nm thick, to prevent oxidation during anneals. Then, a first rapid thermal anneal (RTA) is performed to form the CoSi, TiSi2, or NiSi phase. For example, a 525° C. anneal would react the deposited Co with the underlay Si, converting some of the Si into CoSi.
Thereafter, selective etching of the unreacted metal is performed. For example, the Co that was deposited over non-Si surfaces, such as the dielectric sidewall spacers of the device, cannot react with the Si during the anneal, and therefore would not convert into CoSi. The unreacted Co is etched selectively, leaving the CoSi regions intact.
Finally, a second RTA is performed to form the CoSi2 or TiSi2 low resistive phase. For example, the CoSi is annealed at about 750° C., to form the CoSi2 phase. It is noted that the formation of the CoSi2 phase requires additional consumption of Si from the source and drain regions. The NiSi2 phase has a higher resistivity than NiSi. Thus, a second RTA is not applied in the case of nickel. The silicide forms a junction with the source or drain silicon.
The location of the Silicide/Si junction plays a significant role. At the junction of the contact and the silicon, there is a potential barrier referred to as the Schottky barrier. The Schottky barrier is not desirable, since it leads to a rectifying contact. For example, the Schottky barrier height of CoSi2 on n-type silicon is about 0.64 eV. If the silicon doping is made very high (e.g., such as 5×1019 cm-3), the potential barrier narrows, and electrons can easily tunnel through the thin barrier into the semiconductor. The contact is then referred to as a “tunneling contact”, which performs as an ohmic contact.
Referring to the structure 17 in FIG. 1, to make a good ohmic contact to the source 19a and drain 19b, the silicide/Si junction should form at the peak concentration of the dopants in the source 19a and drain 19b. In addition, the silicide/Si junction should not be deeper than the source/drain junction depth, or otherwise a leakage path may form.
Combining the shallow junction requirement with the requirements associated with the silicide/Si junction position is not trivial. As explained above, the salicide process converts some of the source and drain silicon into silicide. For example, the silicon film thickness that is consumed in the formation of CoSi2 alloy is about 3.64 times thicker than the initial as-deposited Co film.
A Co film of 8 nm thickness would yield a CoSi2 film of about 28 nm, and would consume about 29 nm of silicon. On the other hand, the source and drain junction depth is projected to be about 20 nm for devices with a 100 nm gate length (e.g., see the International Technology Roadmap for Semiconductors, 1999 Edition, Semiconductor Industry Association, Executive Summary).
As may be seen by this example, if the junction is made very shallow as required by the semiconductor road map, the silicide film thickness, X silicide, and therefore the silicide/Si junction position, may even exceed the source/drain junction depth. Since the silicide film cannot be made thinner, due to the resistance constraint, the conventional salicide process must be modified to accommodate the shallow junction technology requirement.
In the example of FIG. 1A, the integrated circuit (IC) has a semiconductor 11 with regions of insulators 13 and bare silicon 15. The IC may comprise a complementary metal-oxide semiconductor (CMOS). The bare silicon regions are isolated from other bare silicon regions. A semiconductor device 17 is located on the semiconductor 11. The semiconductor device has source 19a and drain 19b to form regions of patterned metal. As shown in FIG. 1B, an oxide spacer 21 is formed on the sidewalls of the device 17. In FIG. 1C, a layer 23 of metal is deposited on the entire device as a seed layer. The device 17 is then annealed (FIG. 1D) to form self-aligned silicides 25 (i.e., salicide) under the seed layer 23. Finally (FIG. 1E), any unreacted metal and by products are removed.
The ability to make large arrays of metal on silicon could provide vertical vias, hard masks for vertical etching, or even single electron transistors given the size and spacing of these arrays of metal clusters. In addition, by not having the constraint of a seed layer, wires or interconnects also may be plated. Thus, improvements in electroplating metals for semiconductor applications continue to be of interest.
The embodiments disclosed herein differ from known semiconductor devices in at least two ways. First, embodiments of solutions disclosed herein may comprise vertical transistors rather than conventional lateral transistors. Second, conventional solutions use a material to form the gate completely from block copolymers. In contrast, the embodiments disclosed herein form at least the source and drain contacts, but do not engineer the gate insulation material.